Abstract | ||
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With the advent of portable and high-density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. Optimization for low power can be applied at many different levels of the design hierarchy to ensure a substantial power reduction. In this paper, we propose a post-mapping technique that can reduce the power dissipation by performing gate resizing. This technique consists of replacing some gates of the circuit with devices in a complete cell library having smaller area and, therefore, smaller gate capacitance with lower power consumption. The slack time of each gate in the circuit is first computed to determine the set of gates that can be down-sized. A global optimization procedure for low power, which is based on integer linear programming and the simplex method, is then applied to determine the best overall gate resizing solution. Experimental results on benchmark circuits have shown a power reduction in the range 2.8–27.9% compared to circuits without resizing. The most relevant features of our technique are that it is applicable to large digital circuits and gives an optimal resizing solution in a short computation time (no more than 15.8s). |
Year | DOI | Venue |
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1997 | 10.1016/S0167-9260(97)00024-2 | Integration |
Keywords | Field | DocType |
gate resizing,high reduction,non-iterative gate,power consumption,low-power optimization,low power,global optimization,digital circuits,power dissipation,simplex method | Digital electronics,Global optimization,Computer science,Circuit design,Electronic engineering,Integer programming,Electronic circuit,Gate equivalent,Integrated circuit,Very-large-scale integration,Electrical engineering | Journal |
Volume | Issue | ISSN |
24 | 1 | Integration, the VLSI Journal |
Citations | PageRank | References |
1 | 0.37 | 12 |
Authors | ||
4 |
Name | Order | Citations | PageRank |
---|---|---|---|
P. Girard | 1 | 478 | 41.91 |
C. Landrault | 2 | 1 | 0.37 |
S. Pravossoudovitch | 3 | 689 | 54.12 |
D. Severac | 4 | 16 | 1.54 |