Name
Abstract | ||
|---|---|---|
Dynamically reconfigurable logic is becoming an important design unit in SoC system. A method to make the reconfiguration management transparent to software applications is required in order to make easier the design with such devices. In this paper, we present an efficient approach similar to the cache miss and the data replacement in modern computer system for the task. The main advantage is that the reconfiguration can be correctly issued without extra instructions inserted either manually by SW application programmers or automatically by compilers. The approach was validated in a real case design. In the Virtex2P20 implementation platform, the resource overhead was 2.45% in terms of the number of LUTs. Performance is measured in cycle-accurate simulation environment. The overhead is about equal when compared with an OS-based equivalent design that uses system calls and critical section code to manage the reconfiguration. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/FPL.2005.1515805 | FPL |
Keywords | Field | DocType |
application program interfaces,run time reconfiguration,soc system,virtex2p20 implementation,reconfigurable architectures,system-on-chip,software applications,logic design,reconfigurable logic,reconfiguration management,data replacement,embedded systems,cache miss,critical section,system on chip | Logic synthesis,System on a chip,Computer science,Critical section,Parallel computing,Real-time computing,Compiler,Software,Cache miss,Control reconfiguration,Operating system,Embedded system | Conference |
ISBN | Citations | PageRank |
0-7803-9362-7 | 0 | 0.34 |
References | Authors | |
13 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yang Qu | 1 | 103 | 10.67 |
| Juha-Pekka Soininen | 2 | 147 | 23.41 |
| Jari Nurmi | 3 | 556 | 83.87 |