Name
Abstract | ||
|---|---|---|
We report on a new, reconfigurable, packet-based, embedded test protocol that supports several popular test methodologies (boundary scan, full-scan and BIST among others) for testing multi-core SOCs. Unlike the conventional SOC test methods that require use of an expensive automatic test equipment, our proposal uses on-chip embedded cores that serve as microtesters. The protocol is implemented using two embedded cores: Test Server and Test Client. The Test Server delivers test parameters as test packets to Test Clients. Experimental results show that our new test protocol can be implemented with low (less than 2%) hardware overhead. Since hardware overhead for our test protocol does not grow as the size of SOCs, it will be even lower for large SOCs. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ASPDAC.2004.1337572 | ASP-DAC |
Keywords | Field | DocType |
hardware overhead,popular test methodology,expensive automatic test equipment,re-configurable embedded core test,conventional soc test method,test server,new test protocol,embedded test protocol,test protocol,test parameter,test packet,chip,automatic test equipment,test methods,system on chip | Test harness,Boundary scan,Automatic test pattern generation,System on a chip,Automatic test equipment,Computer science,White-box testing,Real-time computing,Test compression,Embedded system,Built-in self-test | Conference |
ISSN | ISBN | Citations |
2153-6961 | 0-7803-8175-0 | 2 |
PageRank | References | Authors |
0.53 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seongmoon Wang | 1 | 605 | 48.50 |
| Srimat T. Chakradhar | 2 | 2492 | 185.94 |
| Kedarnath J. Balakrishnan | 3 | 160 | 10.85 |