Name
Abstract | ||
|---|---|---|
Boundary-scan testing is used to overcome many of the testability issues facing today's higher density designs. In the past, boundary-scan has been used successfully to perform interconnect testing between boundary-scan supporting devices. There has been an increased use of testing clusters of non-boundary-scan devices that are surrounded by boundary-scan access at the edge of the circuit both in manufacturing and system test. Boundary-scan is also being used to perform cluster testing of memory devices that do not support boundary-scan directly. These specialized boundary-scan tests are written to emulate a functional test pattern flow which requires a relatively precise control of the timing constraints in a synchronous clock window for Synchronous Dynamic Random Access Memory (SDRAM). New interface architectures are also stressing the timing constraints available from a boundary-scan based test. This paper discusses the issues impeding boundary-scan based memory testing and suggests some alternative methods for testing these memory devices when boundary-scan testing is unattainable. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TEST.2008.4700645 | 2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS |
Keywords | Field | DocType |
testing,dynamic random access memory,functional testing,memory management,field programmable gate arrays | Boundary scan,Testability,Orthogonal array testing,System testing,Computer science,Field-programmable gate array,Synchronous dynamic random-access memory,Real-time computing,White-box testing,Memory management,Computer hardware,Embedded system | Conference |
ISSN | Citations | PageRank |
1089-3539 | 1 | 0.37 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bradford G. Van Treuren | 1 | 4 | 2.47 |
| Chen-Huan Chiang | 2 | 53 | 7.33 |
| Kenneth Honaker | 3 | 1 | 0.37 |