Name
Abstract | ||
|---|---|---|
This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal of minimizing the test cost. Best and worst case bounds are established for the performance of a reordered sequence compared to the original sequence of test application. SEMATECH test data and simulation results are used throughout to illustrate the ideas. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ASPDAC.2002.994969 | VLSI Design |
Keywords | Field | DocType |
reordered sequence,worst case bound,permuting test vector,test efficiency,test cost,simulation result,defect coverage,original sequence,sematech test data,test reordering,novel method,test application,vlsi tests,design for testability,cost benefit analysis,cost function,computer science,vlsi,compaction,automatic test pattern generation,fabrication,silicon,testing,routing,very large scale integration,automation,logic synthesis,permutation test | Logic synthesis,Automatic test pattern generation,Fault coverage,Computer science,Permutation,Electronic engineering,Test efficiency,Test data,Test compression,Computer engineering,Very-large-scale integration,Reliability engineering | Conference |
ISBN | Citations | PageRank |
0-7695-1441-3 | 0 | 0.34 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hailong Cui | 1 | 15 | 1.76 |
| Sharad C. Seth | 2 | 671 | 93.61 |
| Shashank K. Mehta | 3 | 45 | 11.65 |