Name
Title | ||
|---|---|---|
CriAS: A performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture |
Abstract | ||
|---|---|---|
In deep submicron era, wire delay is no longer negligible and is dominating the system performance. Several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures to cope with the increasing wire delay by allowing on-chip multicycle communication. In this paper, we present a new performance-driven criticality-aware synthesis flow CriAS targeting regular distributed register architectures. CriAS features a hierarchical binding strategy and a coarse-grained placer for minimizing the number of critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that 19% overall performance improvement can be achieved on average as compared to the previous work. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ASPDAC.2009.4796443 | ASP-DAC |
Keywords | Field | DocType |
integrated memory circuits,on-chip multicycle communication architecture,deep submicron era,later placement phase,flow crias,critical global data transfers,integrated circuit interconnections,register architecture,hierarchical binding strategy,performance-driven criticality-aware synthesis flow,binding stage,new performance-driven criticality-aware synthesis,increasing wire delay,critical component,crias,integrated circuit design,critical global data transfer,wire delay,detailed physical placement information,distributed register architectures,chip,data transfer,schedules,computer architecture,registers,system performance | Communication architecture,Locality,Computer science,Flow (psychology),Real-time computing,Electronic engineering,Integrated circuit design,Schedule,Criticality,Embedded system,Performance improvement | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-2749-9 | 4 |
PageRank | References | Authors |
0.41 | 11 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chia-I Chen | 1 | 13 | 2.02 |
| Juinn-Dar Huang | 2 | 270 | 27.42 |