Name
Abstract | ||
|---|---|---|
A delay-locked loop based clock generator with the multiplication ratios from 13 to 20 using a programmable dynamic frequency divider is presented in this paper. Compared with the conventional dividers, a dynamic frequency divider achieves both low transistor count and low power consumption. This design employs re-circulating DLL structure to remove the phase noise accumulated within each reference period, and avoid the effect of the mismatch among delay stages to improve the output jitter performance. Implemented in 0.18 um CMOS technology, this design operates up to 2.9 GHz. With a reference signal from an RF signal generator, the measured phase noise for the carrier frequency of 2.795 GHz is -110 dBc/Hz at 100 kHz offset, and the RMS timing fitter at 2 GHz is 3.68 pS. The circuit consumes approximately 19 mW at 2 GHz output and occupies an area of less than 0.06 mm(2). |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/CCECE.2006.277703 | 2006 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-5 |
Keywords | Field | DocType |
clock generator, DLL, PLL, timing jitter | Phase-locked loop,Clock generator,Frequency divider,Computer science,Signal generator,Phase noise,CMOS,Electronic engineering,dBc,Jitter | Conference |
ISSN | Citations | PageRank |
0840-7789 | 0 | 0.34 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Qingjin Du | 1 | 37 | 7.26 |
| Jingcheng Zhuang | 2 | 76 | 12.41 |
| Tad A. Kwasniewski | 3 | 43 | 13.71 |