Tad A. Kwasniewski - Citegraph

Author Info

Name	Affiliation	Papers
TAD A. KWASNIEWSKI	Carleton Univ, Dept Elect, Ottawa, ON K1S 5B6, Canada	18
Collaborators	Citations	PageRank
30	43	13.71
Referers	Referees	References
105	93	28

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100105

Publications (18 rows)

Collaborators (30 rows)

Referers (100 rows)

Referees (93 rows)

Title	Citations	PageRank	Year
A DLL-based fractional-N frequency synthesizer with a programmable injection clock	2	0.55	2012
Optimized LNA for analog RF front-end circuit in brain-machine interface	0	0.34	2010
A 0.18-μm CMOS clock and data recovery circuit with reference-less dual loops	2	0.56	2008
A 4ghz Low Complexity Adpll-Based Frequency Synthesizer In 90nm Cmos	7	0.99	2007
A Timing Jitter Reduction Technique In A Cyclic Injection Clock Multiplier For Data Communication System	0	0.34	2006
An eye detection technique for clock and data recovery applications	0	0.34	2006
A 0.18-μm CMOS receiver with decision-feedback equalization for backplane applications	1	0.40	2006
A Low Phase Noise Dll Clock Generator With A Programmable Dynamic Frequency Divider	0	0.34	2006
A 0.18-Mu M Cmos Clock And Data Recovery Circuit With Extended Operation Range	0	0.34	2006
An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur.	0	0.34	2006
A 0.18µm CMOS transceiver design for high-speed backplane data communications	0	0.34	2005
A signal integrity-based link performance simulation platform	5	0.71	2005
Behavioral Test Benches for Digital Clock and Data Recovery Circuits using Verilog-A	1	0.38	2005
2.4 GHz RF down-conversion mixers in standard CMOS technology	0	0.34	2004
Design and comparison of CMOS Current Mode Logic latches	6	1.00	2004
A Quadrature Output Voltage Controlled Ring Oscillator Based On Three-Stage Sub-Feedback Loops	11	2.64	1999
Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis	8	3.44	1999
A low power, single chip realization of a low-speed, low-delay CELP coder/decoder for indoor wireless systems	0	0.34	1994

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