Name
Abstract | ||
|---|---|---|
For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1093/ietele/e90-c.6.1307 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
digitally controlled PLL, clock-period comparator, loop characteristic, loop filter | Phase-locked loop,Comparator,Spice,Lock (computer science),PLL multibit,Electronic engineering,Voltage-controlled oscillator,Engineering,Digital control,Phase locking | Journal |
Volume | Issue | ISSN |
E90C | 6 | 1745-1353 |
Citations | PageRank | References |
1 | 0.40 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yukinobu Makihara | 1 | 1 | 0.40 |
| M. Ikebe | 2 | 47 | 13.63 |
| Eiichi Sano | 3 | 7 | 6.98 |