M. Ikebe - Citegraph

Author Info

Name	Affiliation	Papers
M. IKEBE	Hokkaido Univ, Dept Elect Engn, Kita Ku, Sapporo, Hokkaido 060, Japan	35
Collaborators	Citations	PageRank
82	47	13.63
Referers	Referees	References
178	343	100

Search Limit

100343

Publications (35 rows)

Collaborators (82 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark	0	0.34	2022
Warm-cool color-based high-speed decolorization: an empirical approach for tone mapping applications.	0	0.34	2021
Quantification Of Joint Space Width Difference On Radiography Via Phase-Only Correlation (Poc) Analysis: A Phantom Study Comparing With Various Tomographical Modalities Using Conventional Margin-Contouring	0	0.34	2021
An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA	0	0.34	2020
5.8 A 32×32-Pixel 0.9THz Imager with Pixel-Parallel 12b VCO-Based ADC in 0.18μm CMOS	0	0.34	2019
Fpga-Based Annealing Processor With Time-Division Multiplexing	0	0.34	2019
Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band	0	0.34	2019
Dither Nn: Hardware/Algorithm Co-Design For Accurate Quantized Neural Networks	0	0.34	2019
Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions	1	0.40	2018
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing.	0	0.34	2018
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.	15	0.85	2018
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA.	1	0.40	2018
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators	0	0.34	2018
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware	1	0.43	2018
Accelerating deep learning by binarized hardware.	0	0.34	2017
In-memory area-efficient signal streaming processor design for binary neural networks	1	0.38	2017
A Time-Division Multiplexing Ising Machine on FPGAs.	0	0.34	2017
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training	0	0.34	2017
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces.	0	0.34	2016
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer	3	0.52	2015
Recent Progress In The Technology Linking Sensors And Digital Circuits	0	0.34	2014
A 12-bit, 5.5-μW single-slope ADC using intermittent working TDC with multi-phase clock signals	0	0.34	2014
Accuracy Improvement Of Histogram-Based Image Filtering	3	0.43	2013
A 11b 5.1µW multi-slope ADC with a TDC using multi-phase clock signals	0	0.34	2012
A 0.6-4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network.	1	0.41	2011
Column parallel single-slope ADC with time to digital converter for CMOS imager	2	0.46	2010
O(1) bilateral filtering with low memory usage	7	0.54	2010
A 3.1-10.6 GHz RF CMOS circuits monolithically integrated with dipole antenna.	0	0.34	2009
Local adaptive tone mapping with composite multiple gamma functions	2	0.40	2009
Evaluation Of Digitally Controlled Pll By Clock-Period Comparison	1	0.40	2007
Cmos Image Sensor Using Negative-Feedback Resetting To Obtain Variably Smoothed Images	0	0.34	2006
A Quadrilateral-Object Composer For Binary Images With Reaction-Diffusion Cellular Automata	1	0.41	2005
A Digital Vision Chip For Early Feature Extraction With Rotated Template-Matching Ca	2	0.40	2005
A Novel Cmos Circuit For Depressing Synapse And Its Application To Contrast-Invariant Pattern Classification And Synchrony Detection	6	0.47	2004
nu-MOS cellular-automaton devices for intelligent image sensors	0	0.34	1998