Name
Title | ||
|---|---|---|
A bottleneck prediction and rolling horizon scheme combined dynamic scheduling algorithm for semiconductor wafer fabrication |
Abstract | ||
|---|---|---|
Semiconductor wafer fabrication is a very complicated manufacturing system which is characterized by re-entrance production flow, complicated constraints, and dynamic and uncertain environment. Bottleneck is the key factor to the wafer fabrication which has essential influence on the throughput rate, cycle time, time-delivery rate, etc. The optimal scheduling policies for bottleneck machines are conducive to cost decreasing, throughput target achieving and production-resource scheduling improving. In this paper, considering the characteristic information concerning bottleneck and the whole production line, a bottleneck prediction method based on improved adaptive network-based fuzzy inference system (ANFIS) is presented by predicting the wait time of the lot in workstation buffer and the workstation load. Then, based on the obtained bottleneck and directly considering the layer load levels of bottleneck and due date, we proposed a dynamic different layer bottleneck-based scheduling algorithm which includes releasing policy and dispatching algorithm for preventing starvation of bottleneck, balancing work in process (WIP) and higher throughput. Applied to a simulation wafer fabrication, our proposed bottleneck prediction method and bottleneck-based scheduling algorithm can reduced the cycle time and improve machine utility compared with other common heuristic scheduling method. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ICNSC.2014.6819600 | ICNSC |
Keywords | DocType | ISSN |
time-delivery rate,dispatching,fuzzy reasoning,dynamic different layer bottleneck-based scheduling algorithm,bottleneck starvation prevention,semiconductor wafer fabrication,scheduling,production engineering computing,reentrance production flow,adaptive network-based fuzzy inference system,due date,manufacturing systems,production line,dynamic scheduling algorithm,workstation load,workstation buffer,complicated manufacturing system,throughput rate,semiconductor technology,wip balancing,optimal scheduling policies,anfis,dispatching algorithm,work in process balancing,semiconductor device manufacture,complicated constraints,cycle time reduction,work in progress,bottleneck prediction method,wafer fabrication simulation,wait time prediction,machine utility,bottleneck machines,production-resource scheduling,releasing policy,rolling horizon scheme,cost reduction,fabrication,dynamic scheduling,workstations,semiconductor device modeling,job shop scheduling,throughput | Conference | 1810-7869 |
Citations | PageRank | References |
2 | 0.42 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jijie Deng | 1 | 2 | 0.42 |
| Cao Zhengcai | 2 | 42 | 16.38 |
| Min Liu | 3 | 536 | 33.56 |