Name
Title | ||
|---|---|---|
Analytical logical effort formulation for minimum active area under delay constraints. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/SBCCI.2013.6644872 | SBCCI |
Keywords | Field | DocType |
low power electronics | Delay calculation,Capacitance,Dissipation,Computer science,Electronic engineering,Minification,Logical effort,MOSFET,Transistor,Low-power electronics | Conference |
Citations | PageRank | References |
0 | 0.34 | 15 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Caio G. P. Alegretti | 1 | 0 | 0.34 |
| Vinícius Dal Bem | 2 | 19 | 4.07 |
| Renato P. Ribas | 3 | 204 | 33.52 |
| André Inácio Reis | 4 | 134 | 21.33 |