Paper Info
Title
A core generator for arithmetic cores and testing structures with a network interface
Abstract
We present Eudoxus, a tool for generation of architectural variants for arithmetic soft cores and testing structures targeting a wide variety of functions, operand sizes and architectures. Eudoxus produces structural and synthesizable VHDL and/or Verilog descriptions for: (a) several arithmetic operations including addition, subtraction, multiplication, division, squaring, square rooting and shifting, and (b) several testing structures that can be used as test pattern generators and test response compactors. Interaction with the user is made through a network interface. Since the end user is presented with a variety of unencrypted structural cores, each one describing an architecture with its own area, delay and power characteristics, he can choose the one that best fits his specific needs which he can further optimize or customize. Therefore, designs utilizing these cores arc completed in less time and with less effort.
Year
DOI
Venue
2006
10.1016/j.sysarc.2004.12.006
Journal of Systems Architecture
Keywords
Field
DocType
verilog description,wide variety,testing structure,arithmetic soft core,arithmetic core,end user,test response compactors,core generator,unencrypted structural core,network interface,arithmetic operation,test pattern generator,present eudoxus
End user,Computer science,Operand,Parallel computing,Arithmetic,Real-time computing,Multiplication,VHDL,Verilog,Subtraction,Square rooting,Network interface
Journal
Volume
Issue
ISSN
52
1
Journal of Systems Architecture
Citations 
PageRank 
References 
4
0.57
22
Authors
7
Name
Order
Citations
PageRank
dimitris bakalis18614.35
K. D. Adaos2152.88
D. Lymperopoulos371.00
Maciej Bellos4234.03
H. T. Vergos55311.37
G. Ph. Alexiou6203.70
D. Nikolos729131.38