Name
Abstract | ||
|---|---|---|
This paper presents a new approach to test pattern generation for sequential circuits modeled as finite state machines. Based on a functional fault model, only a restricted set of transitions of the finite state machine (FSM) is considered for the purpose of testing. A new state discriminating sequence, referred to as EUIO is proposed. Overlapping is accomplished to reduce the test length. In most cases, test length and CPU time requirements are substantially lower compared with gate-level ATPGs. Techniques are a lso introduced to p reserve a high fault coverage. Evaluation on MCNC benchmarks has s hown the e ffectiveness of the test algorithm both at functional and gate levels, while achieving in most cases 100% coverage of single stuck-at faults. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1016/0167-9260(96)00006-5 | Integration |
Keywords | Field | DocType |
distinguishing sequences,sequential circuit,functional test generation,test pattern generation,functional testing,fault model,fault coverage,finite state machine,sequential circuits | Automatic test pattern generation,Sequential logic,Fault coverage,Computer science,CPU time,Algorithm,Electronic engineering,Real-time computing,Finite-state machine,Test compression,Fault model,AND gate | Journal |
Volume | Issue | ISSN |
20 | 3 | Integration, the VLSI Journal |
Citations | PageRank | References |
8 | 0.65 | 26 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Giacomo Buonanno | 1 | 100 | 12.63 |
| F. Fummi | 2 | 201 | 26.93 |
| D. Sciuto | 3 | 1720 | 176.61 |
| F. Lombardi | 4 | 232 | 24.13 |