Paper Info
Title
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning
Abstract
Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to more readily incorporate FPGAs in their designs. FPGA vendors have begun providing configurable soft processor cores that can be synthesized onto their FPGA products. While FPGAs with soft processor cores provide designers with increased flexibility, such processors typically have degraded performance and energy consumption compared to hard-core processors. Previously, we proposed warp processing, a technique capable of optimizing a software application by dynamically and transparently re-implementing critical software kernels as custom circuits in on-chip configurable logic. In this paper, we study the potential of a MicroBlaze soft-core based warp processing system to eliminate the performance and energy overhead of a soft-core processor compared to a hard-core processor. We demonstrate that the soft-core based warp processor achieves average speedups of 5.8 and energy reductions of 57% compared to the soft core alone. Our data shows that a soft-core based warp processor yields performance and energy consumption competitive with existing hard-core processors, thus expanding the usefulness of soft processor cores on FPGAs to a broader range of applications.
Year
DOI
Venue
2005
10.1109/DATE.2005.38
Computing Research Repository
Keywords
Field
DocType
fpga product,warp processor,soft-core processor,fpga configurable logic capacity,energy consumption,dynamic hardware,fpga cost,configurable soft processor core,warp processor yields performance,fpga soft processor,hard-core processor,software partitioning,soft processor core,fpga,degradation,field programmable gate arrays,process design,logic design,speedup,chip,hardware,application software,field programmable gate array,optimization
Logic synthesis,MicroBlaze,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Software,Application software,Energy consumption,Multi-core processor,Embedded system,Reconfigurable computing
Conference
Volume
ISSN
ISBN
abs/0710.4
1530-1591
0-7695-2288-2
Citations 
PageRank 
References 
43
2.18
17
Authors
2
Name
Order
Citations
PageRank
Roman Lysecky160560.43
Frank Vahid22688218.00