Name
Abstract | ||
|---|---|---|
As networking technology advances, the gap between network bandwidth and network processing power widens. Information security issues add to the need for developing high-performance network processing hardware, particularly that for real-time processing of cryptographic algorithms. This paper presents a configurable architecture for Advanced Encryption Standard (AES) encryption, whose major building blocks are a group of AES processors. Each AES processor provides 219 block cipher schemes with a novel on-the-fly key expansion design for the original AES algorithm and an extended AES algorithm. In this multicore architecture, the memory controller of each AES processor is designed for the maximum overlapping between data transfer and encryption, reducing interrupt handling load of the host processor. This design can be applied to high-speed systems since its independent data paths greatly reduces the input/output bandwidth problem. A test chip has been fabricated for the AES architecture, using a standard 0.25-µm CMOS process. It has a silicon area of 6.29 mm2, containing about 200,500 logic gates, and runs at a 66-MHz clock. In electronic codebook (ECB) and cipher-block chaining (CBC) cipher modes, the throughput rates are 844.9, 704, and 603.4 Mb/s for 128-, 192-, and 256-b keys, respectively. In order to achieve 1-Gb/s throughput (including overhead) at the worst case, we design a multicore architecture containing three AES processors with 0.18- m CMOS process. The throughput rate of the architecture is between 1.29 and 3.75 Gb/s at 102 MHz. The architecture performs encryption and decryption of large data with 128-b key in CBC mode using on-the-fly key generation and composite field S-box, making it more cost effective (with better thousand-gate/gigabit-per-second ratio) than conventional methods. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TVLSI.2009.2013231 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
throughput rate,original aes algorithm,aes processor,flexible security,m cmos process,aes architecture,256-b key,multicore architecture,configurable architecture,128-b key,multi-core configurable aes architecture,extended aes algorithm,hardware,interrupts,logic gate,logic design,cryptography,algorithm design and analysis,bandwidth,real time processing,cmos integrated circuits,encryption,information security,cost effectiveness,computer network security,memory controller,multicore processing,block cipher,advanced encryption standard,throughput,input output,process design,network security,chip,cipher block chaining,data transfer | Cipher,Block cipher,Computer science,Advanced Encryption Standard,AES instruction set,Electronic engineering,Real-time computing,Encryption,AES implementations,Encryption software,Memory architecture,Embedded system | Journal |
Volume | Issue | ISSN |
18 | 4 | 1063-8210 |
Citations | PageRank | References |
20 | 0.98 | 23 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mao-Yin Wang | 1 | 47 | 3.51 |
| Chih-Pin Su | 2 | 145 | 9.63 |
| Chia-Lung Horng | 3 | 28 | 1.46 |
| Wu, Cheng-Wen | 4 | 1843 | 170.44 |
| Chih-Tsun Huang | 5 | 673 | 54.07 |