Name
Title | ||
|---|---|---|
A Cascaded Folding Adc Based On Fast-Settling 3-Degree Folders With Enhanced Reset Technique |
Abstract | ||
|---|---|---|
A 7 bit 10 Gsps Cascaded Folding ADC is presented This ADC employs cascaded folding architecture with 3-degree folders A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1 2 V and 2 5 V supplies and has a SNR of 38 dB |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1587/transele.E93.C.288 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
ADC, folding, interpolation, reset, averaging, error correction | Settling,Interpolation,Signal-to-noise ratio,Electronic engineering,Cmos process,Error detection and correction,Shuffling,Engineering,Electrical engineering,Low-power electronics,Power consumption | Journal |
Volume | Issue | ISSN |
E93C | 3 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Koichi Ono | 1 | 58 | 4.84 |
| Takeshi Ohkawa | 2 | 21 | 16.24 |
| Masahiro Segami | 3 | 0 | 0.34 |
| Masao Hotta | 4 | 30 | 9.59 |