Takeshi Ohkawa - Citegraph

Author Info

Name	Affiliation	Papers
TAKESHI OHKAWA	Utsunomiya Univ, Grad Sch Engn, Utsunomiya, Tochigi 3218585, Japan	42
Collaborators	Citations	PageRank
62	21	16.24
Referers	Referees	References
63	352	116

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100352

Publications (42 rows)

Collaborators (62 rows)

Referers (63 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Genetic Node-Mapping Methods For Rapid Collective Communications	0	0.34	2020
Genetic Node-Mapping Methods for Rapid Collective Communications.	0	0.34	2020
Accelerating Large-Scale Interconnection Network Simulation By Cellular Automata Concept	0	0.34	2019
Fast Computation With Efficient Object Data Distribution For Large-Scale Hologram Generation On A Multi-Gpu Cluster	0	0.34	2019
Directive-Based Parallelization of For-Loops at LLVM IR Level	0	0.34	2019
Realization and Preliminary Evaluation of MPI Runtime Environment on Android Cluster.	0	0.34	2019
High level synthesis of ROS protocol interpretation and communication circuit for FPGA	0	0.34	2019
Automatic Generation Tool Of Fpga Components For Robots	1	0.41	2019
Data Distribution Method for Fast Giga-scale Hologram Generation on a Multi-GPU Cluster.	0	0.34	2018
A Genetic Approach For Accelerating Communication Performance By Node Mapping	0	0.34	2018
Overcoming the difficulty of large-scale CGH generation on multi-GPU cluster.	0	0.34	2018
Fpga Components For Integrating Fpgas Into Robot Systems	4	1.16	2018
An Implementation of LLVM Pass for Loop Parallelization Based on IR-Level Directives	0	0.34	2018
Development of a Robot Car by Single Line Search Method for White Line Detection with FPGA	1	0.43	2018
A Static Packet Scheduling Approach For Fast Collective Communication By Using Pso	0	0.34	2017
Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus	0	0.34	2017
Acceleration Of Large-Scale Cgh Generation Using Multi-Gpu Cluster	1	0.48	2017
Acceleration of Publish/Subscribe Messaging in ROS-compliant FPGA Component.	0	0.34	2017
Large-Scale Interconnection Network Simulation Methods Based on Cellular Automata	0	0.34	2017
A Translation Method Of Arm Machine Code To Llvm-Ir For Binary Code Parallelization And Optimization	0	0.34	2017
Performance of Android Cluster System Allowing Dynamic Node Reconfiguration.	1	0.38	2017
Architecture exploration of intelligent robot system using ros-compliant FPGA component.	2	0.39	2016
cReComp: Automated Design Tool for ROS-Compliant FPGA Component	0	0.34	2016
An Android Cluster System Capable Of Dynamic Node Reconfiguration	1	0.40	2015
Relaxing Heavy Congestion by State Propagation.	1	0.37	2015
Efficient Translation and Execution Method for Automated Parallel Processing System by Using Valgrind.	0	0.34	2015
Performance Improvement of Large-Scale Interconnection Network Simulator by Using GPU.	0	0.34	2015
Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems	0	0.34	2015
Empirical performance study of speculative parallel processing on commercial multi-core CPU with hardware transactional memory.	0	0.34	2015
Entropy Throttling: Towards Global Congestion Control of Interconnection Networks.	2	0.40	2015
Proposal of Highly Efficient Memory Access Method Using Locked-Cache on Soft-Core Processor with SIMD Operations.	0	0.34	2015
Efficient Data Communication Using Dynamic Switching of Compression Method	0	0.34	2013
Exploration of Highly Accurate Path Prediction Mechanism Using Detailed Path History	0	0.34	2013
Runtime Overhead Reduction in Automated Parallel Processing System Using Valgrind	3	0.51	2013
A Cellular Automata Approach for Large-Scale Interconnection Network Simulation	0	0.34	2013
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application	0	0.34	2013
A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluation.	0	0.34	2013
Comparative Study of Path Prediction Method for Speculative Loop Execution	1	0.43	2012
Proposal of Incremental Software Simulation for Reduction of Evaluation Time	0	0.34	2012
COOL interconnect low power interconnection technology for scalable 3D LSI design	3	0.74	2011
A Cascaded Folding Adc Based On Fast-Settling 3-Degree Folders With Enhanced Reset Technique	0	0.34	2010
The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration	0	0.34	2004