Name
Abstract | ||
|---|---|---|
SIMD architectures are less efficient for applications with the diverse control-flow behavior, which can be mainly attributed to the requirement of the identical control-flow. In this paper, we propose a novel instruction shuffle scheme that features an efficient control-flow handling mechanism. The cornerstones are composed of a shuffle source instruction buffer array and an instruction shuffle unit. The shuffle unit can concurrently deliver instructions of multiple distinct control-flows from the instruction buffer array to eligible SIMD lanes. Our instruction shuffle scheme combines the best attributes of both the SIMD and MIMD execution paradigms. Experimental results show that, an average performance improvement of 86% can be achieved, at a cost of only 5.8% area overhead. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/L-CA.2011.34 | Computer Architecture Letters |
Keywords | Field | DocType |
achieving mimd-like performance,instruction buffer array,simd architecture,eligible simd lane,diverse control-flow behavior,instruction shuffle unit,novel instruction shuffle scheme,instruction shuffle,simd architectures,efficient control-flow handling mechanism,shuffle unit,shuffle source instruction buffer,instruction shuffle scheme,resource management,kernel,vectors,instruction sets,simd,process control,parallel processing,scalability | Kernel (linear algebra),Computer architecture,Instruction register,Instruction set,Computer science,Parallel computing,SIMD,Real-time computing,Process control,Performance improvement,Scalability,MIMD | Journal |
Volume | Issue | ISSN |
11 | 2 | 1556-6056 |
Citations | PageRank | References |
1 | 0.36 | 0 |
Authors | ||
7 | ||