Yaohua Wang - Citegraph

Author Info

Name	Affiliation	Papers
YAOHUA WANG	Natl Univ Def Technol, Sch Comp, Changsha 410073, Hunan, Peoples R China	39
Collaborators	Citations	PageRank
113	44	14.23
Referers	Referees	References
162	1037	384

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Publications (39 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators	0	0.34	2022
MT-3000: a heterogeneous multi-zone processor for HPC	0	0.34	2022
HeSA - Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators.	0	0.34	2021
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations	2	0.35	2021
Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks	0	0.34	2021
Universal Pre-Calculating Structure: Reducing Complexity of Ising Chips with Arbitrary Connectivity	0	0.34	2021
Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions	1	0.36	2021
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching	2	0.35	2020
Deviation based clustering for unsupervised person re-identification.	1	0.36	2020
Novel Design Strategy Toward A2 Trojan Detection Based on Built-In Acceleration Structure	0	0.34	2020
CMSA: Configurable Multi-directional Systolic Array for Convolutional Neural Networks	0	0.34	2020
A Lifelong Health Monitoring Framework in Processors: Work-in-Progress	0	0.34	2020
Hierarchical Clustering With Hard-Batch Triplet Loss for Person Re-Identification	7	0.48	2020
A Specification-Based Semi-Formal Functional Verification Method By A Stage Transition Graph Model	0	0.34	2019
ITAP: Idle-Time-Aware Power Management for GPU Execution Units.	1	0.35	2019
The Evaluation of DCNN on Vector-SIMD DSP.	0	0.34	2019
Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices.	0	0.34	2019
FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives.	7	0.46	2018
Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions.	1	0.35	2018
Advancing CMOS-Type Ising Arithmetic Unit into the Domain of Real-World Applications.	1	0.37	2018
Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration.	9	0.39	2018
Iteration Interleaving-Based SIMD Lane Partition.	1	0.36	2016
Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs	1	0.41	2016
FT-Matrix: A Coordination-Aware Architecture for Signal Processing	3	0.43	2014
Redefining the relationship between scalar and parallel units in SIMD architectures	0	0.34	2013
A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments	1	0.35	2013
A Novel Qpp Interleaver For Parallel Turbo Decoder	0	0.34	2013
Dual-Core Framework: Eliminating The Bottleneck Effect Of Scalar Kernels On Simd Architectures	1	0.48	2013
Breaking The Performance Bottleneck Of Sparse Matrix-Vector Multiplication On Simd Processors	1	0.48	2013
Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes	0	0.34	2012
Architectural Implications for SIMD Processors in the Wireless Communication Domain	0	0.34	2012
Cmrf: A Configurable Matrix Register File For Accelerating Matrix Operations On Simd Processors	1	0.37	2012
Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures	1	0.36	2012
Suca: A Scalable Unicore Architecture With Novel Instruction Encoding And Distributed Execution Control	0	0.34	2011
Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle	0	0.34	2011
Lp2d: A Novel Low-Power 2d Memory For Sliding-Window Applications In Vector Dsps	0	0.34	2011
AIFSP: An Adaptive Instruction Flow Stream Processor	0	0.34	2011
Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs	1	0.39	2011
Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform	1	0.35	2010