Name
Abstract | ||
|---|---|---|
We present a graph model and an ILP model for optimal TAM design for transparency-based SoC testing. The proposed method is an extension of [12] so that not only the system-level cost but also the core-level cost can be simultaneously taken into consideration during the optimization process. We also relax the constraints by considering test data flows and extend it to be able to handle the case where cores cannot be made transparent due to IP protection. The proposed ILP model can represent various problems including the same problem as [12] and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to [12]. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/VTS.2007.78 | VTS |
Keywords | Field | DocType |
optimal tam design,ip protection,core-level cost,proposed ilp model,graph model,better result,transparency-based soc test,tam design,ilp model,system-level cost,switches,linear programming,transparency,design optimization,cost function,system on chip,integer linear programming,testing,throughput,integer programming,graph theory,information science | Graph theory,Transparency (graphic),System on a chip,Computer science,Information science,Electronic engineering,Real-time computing,Integer programming,Linear programming,Throughput,Graph model | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-2812-0 | 1 |
PageRank | References | Authors |
0.36 | 15 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomokazu Yoneda | 1 | 154 | 19.35 |
| Akiko Shuto | 2 | 1 | 0.70 |
| Hideyuki Ichihara | 3 | 96 | 18.92 |
| Tomoo Inoue | 4 | 352 | 47.23 |
| Hideo Fujiwara | 5 | 34 | 3.55 |