Paper Info
Title
Design For Delay Measurement Aimed At Detecting Small Delay Defects On Global Routing Resources In Fpga
Abstract
Small delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, In a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB. For recent FPGAs, we can estimate that the area overhead is approximately 2% or less of the FPGAs.
Year
DOI
Venue
2013
10.1587/transinf.E96.D.1613
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
Keywords
Field
DocType
small delay defects, delay measurement, DVMC (delay value measurement circuit), FPGA (field programmable gate array), global routing resource
Delay calculation,Computer science,Transmission delay,Field-programmable gate array,Real-time computing,Processing delay
Journal
Volume
Issue
ISSN
E96D
8
1745-1361
Citations 
PageRank 
References 
0
0.34
7
Authors
3
Name
Order
Citations
PageRank
Kazuteru Namba111427.93
Nobuhide Takashina200.34
Hideo Ito310017.45