Paper Info
Title
Compact Test Generation Using a Frozen Clock Testing Strategy
Abstract
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach to generating compact test sequences for sequential circuits. Our approach combines a conventional ATPG algorithm, a technique based on the frozen clock testing strategy, and a dynamic compaction method based on a genetic algorithm. The frozen clock strategy temporarily suspends the sequential behavior of the circuit by stopping its clock and applying several vectors to increase the number of faults detected without changing the circuit state. Results show that test sets generated using the new approach are more compact than those generated by previous approaches for many circuits.
Year
Venue
Keywords
2000
JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
automatic test generation,compact test sets,frozen clock testing strategy,sequential circuit testing,test vector compaction
Field
DocType
Volume
Automatic test pattern generation,Vlsi chip,Sequential logic,Dynamic compaction,Computer science,Real-time computing,Test compression,Computer hardware,Electronic circuit,Test strategy,Genetic algorithm,Distributed computing
Journal
16
Issue
ISSN
Citations 
5
1016-2364
2
PageRank 
References 
Authors
0.36
10
2
Name
Order
Citations
PageRank
Elizabeth M. Rudnick186776.37
Miron Abramovici21441117.84