Name
Abstract | ||
|---|---|---|
A new method for state justification is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justification. State-transfer sequences that drive the circuit from the current state to the target state may already be known. Otherwise, genetic engineering of existing state-transfer sequences is required. In both cases, genetic-algorithm-based techniques are used to generate valid state justification sequences for the circuit in the presence of the target fault. This approach achieves extremely high fault coverages, and thus outperforms previous deterministic and simulation-based techniques. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1145/348019.348288 | ACM Trans. Design Autom. Electr. Syst. |
Keywords | Field | DocType |
target state,genetic algorithms,state justification,finite-state-machine traversal,valid state justification sequence,automatic test pattern generation atpg,genetic engineering,test vector,high fault coverage,dynamic state traversal,simulation-based,testing,sequential circuit test generation,sequential circuits,state-transfer sequence,target fault,current state,fault coverage,genetic algorithm,finite state machine | Stuck-at fault,Automatic test pattern generation,Sequential logic,Tree traversal,Fault coverage,Computer science,Algorithm,Genetic algorithm | Journal |
Volume | Issue | ISSN |
5 | 3 | 1084-4309 |
Citations | PageRank | References |
14 | 0.82 | 14 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael S. Hsiao | 1 | 1467 | 132.13 |
| Elizabeth M. Rudnick | 2 | 867 | 76.37 |
| J. H. Patel | 3 | 4577 | 527.59 |