Name
Abstract | ||
|---|---|---|
In this paper, we propose an orthogonal scan chain embedded into the RTL design described by Verilog. We first construct the data path graph from the embedded scan chains and then find all the orthogonal scan paths with the minimum weighted cost. These paths share with original data paths as possible. Finally, we create a stack form to reconstruct all the orthogonal scan paths to manage the I/Os and reduce the length and width of stack form as well as decrease the overheads of area and timing. Experimental results show our RTL orthogonal scan chain approach can save up to 13.8% and 5.1% in area overhead than that of the gate-level scan and functional order RTL scan, respectively. |
Year | Venue | Keywords |
|---|---|---|
2006 | JOURNAL OF INFORMATION SCIENCE AND ENGINEERING | RTL scan,orthogonal scan chain,area overhead,timing overhead,fault coverage |
DocType | Volume | Issue |
Journal | 22 | 6 |
ISSN | Citations | PageRank |
1016-2364 | 0 | 0.34 |
References | Authors | |
9 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chia-chun Tsai | 1 | 109 | 23.04 |
| Hann-cheng Huang | 2 | 0 | 0.34 |
| Trong-yen Lee | 3 | 98 | 20.70 |
| Wen-Ta Lee | 4 | 16 | 5.45 |
| Jan-ou Wu | 5 | 12 | 4.53 |