Paper Info
Title
Estimation of circuit activity considering signal correlations and simultaneous switching
Abstract
This paper presents accurate estimation of signal activity at the internal nodes of CMOS combinational logic circuits. The methodology is based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinational logic synthesis, in order to minimize spurious transitions due to finite propagation delays, it is crucial to balance all signal paths and to reduce the logic depth. As a result of balancing delays through different paths, the inputs to logic gates may switch at approximately the same time. We have developed and implemented an technique to calculate signal probability and switching activity of the CMOS combinational logic circuits. Experimental results show that if simultaneous switching is not considered the switching activities of the internal nodes can be off by more than 100% compared to simulation based techniques. In contrast, our technique is on the average within 2% of logic simulation results.
Year
DOI
Venue
1994
10.1109/ICCAD.1994.629784
ICCAD
Keywords
Field
DocType
signal activity,logic signal,logic depth,circuit activity,logic gate,simultaneous switching,combinational logic synthesis,logic simulation result,internal node,logic gate input,cmos combinational logic circuit,signal correlation,logic synthesis,propagation delay,switches,combinational circuits,capacitance,logic gates,power dissipation,stochastic model
Digital electronics,Logic gate,Sequential logic,Pass transistor logic,Computer science,Logic optimization,Real-time computing,Electronic engineering,Logic level,Logic family,Programmable logic device
Conference
ISSN
ISBN
Citations 
1063-6757
0-89791-690-5
42
PageRank 
References 
Authors
7.72
6
3
Name
Order
Citations
PageRank
Tan-Li Chou118123.80
Kaushik Roy27093822.19
Sharat Prasad39229.55