Name
Abstract | ||
|---|---|---|
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register (RDR) micro-architecture for multi-cycle on-chip communication. An RDR architecture structurally consists of a two-dimensional array of islands, each of which contains a cluster of computational logic and local register files. We also propose a new synthesis methodology based on the RDR architecture. Novel layout-driven architectural synthesis algorithms have been developed for RDR. Application of these algorithms to several real-life benchmarks demonstrates 44% improvement on average in terms of the clock period and 37% improvement on average in terms of the final latency. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1145/640000.640040 | ISPD |
Keywords | Field | DocType |
final latency,novel layout-driven architectural synthesis,local register file,multi-cycle communication,rdr architecture,multiple clock cycle,clock period,global interconnects,new synthesis methodology,data transfer,computational logic,rdr,chip,design,performance,algorithms,interconnect,scheduling,register file,placement | Computational logic,Architecture,Latency (engineering),Scheduling (computing),Computer science,Parallel computing,Interconnection,Timing closure | Conference |
ISBN | Citations | PageRank |
1-58113-650-1 | 19 | 1.29 |
References | Authors | |
17 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jason Cong | 1 | 7069 | 515.06 |
| Yiping Fan | 2 | 456 | 25.67 |
| Xun Yang | 3 | 22 | 1.75 |
| Zhiru Zhang | 4 | 1020 | 71.74 |