Name
Abstract | ||
|---|---|---|
Dynamically reconfigurable co-processors (DRCs) are interesting design alternatives when both flexibility and performance are concerns. However, it is difficult to study the performance impact of including such devices into design when using traditional design methods and tools. In this paper, we present easily adaptable system-level techniques, which are able to perform fast exploration of different reconfiguration. alternatives. A SystemC-based modeling method for DRCs and a high-level synthesis-based estimation tool to support system partitioning are presented. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1007/978-3-540-30117-2_93 | Lecture Notes in Computer Science |
Keywords | Field | DocType |
high level synthesis,design method,adaptive system | System level modeling,Computer science,High-level synthesis,Circuit design,Field-programmable gate array,Design methods,Real-time computing,SystemC,Design space exploration,Control reconfiguration,Embedded system | Conference |
Volume | ISSN | Citations |
3203 | 0302-9743 | 9 |
PageRank | References | Authors |
0.98 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yang Qu | 1 | 103 | 10.67 |
| Kari Tiensyrjä | 2 | 42 | 10.53 |
| Kostas Masselos | 3 | 75 | 11.00 |