Name
Abstract | ||
|---|---|---|
This paper presents a built-in self-test/repair (BISTR) scheme for through-silicon via (TSV) based three-dimension integrated circuits (3D ICs). The proposed BIST structure focuses on the testing of a specific defective TSV by using a critical value of threshold. Then, the test results from BIST will be delivered to the BISR structure for repairing the defective TSV. Additionally, a parallel processing approach is presented of the proposed BISTR scheme to speed up the operations of test and repair. Experimental results demonstrate that the proposed BISTR scheme can achieve the good performance in repair rate and yield with little area overhead penalty. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/APCCAS.2010.5774885 | PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS) |
Keywords | Field | DocType |
3D IC, TSV, BIST, BISR, area overhead, yield | Computer science,Parallel processing,Electronic engineering,Through-silicon via,Three-dimensional integrated circuit,Integrated circuit,Reliability engineering,Maintenance engineering,Benchmark (computing),Built-in self-test,Speedup | Conference |
Citations | PageRank | References |
9 | 0.56 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hung-Yen Huang | 1 | 12 | 0.98 |
| Yu-Sheng Huang | 2 | 9 | 0.56 |
| Chun-Lung Hsu | 3 | 59 | 14.53 |