Chun-Lung Hsu - Citegraph

Author Info

Name	Affiliation	Papers
CHUN-LUNG HSU	Natl Dong Hwa Univ, Dept Elect Engn, Hualien 974, Taiwan	37
Collaborators	Citations	PageRank
74	59	14.53
Referers	Referees	References
187	627	238

Search Limit

100627

Publications (37 rows)

Collaborators (74 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Fault-Aware Dependability Enhancement Techniques for Phase Change Memory	0	0.34	2021
Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering	0	0.34	2021
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling	0	0.34	2021
Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design	0	0.34	2020
Testing of Configurable 8T SRAMs for In-Memory Computing	0	0.34	2020
Fault-Aware Dependability Enhancement Techniques for Flash Memories	0	0.34	2020
Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory	0	0.34	2020
Head-Orientation-Prediction Based on Deep Learning on sEMG for Low-Latency Virtual Reality Application	0	0.34	2020
ECC Caching Techniques for Protecting NAND Flash Memories	0	0.34	2020
Testing of In-Memory-Computing 8T SRAMs	0	0.34	2019
Testing stuck-open faults of priority address encoder in content addressable memories.	0	0.34	2019
Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM.	0	0.34	2019
Multiple-Wearable-Sensor-Based Gait Classification and Analysis in Patients with Neurological Disorders.	4	0.44	2018
Diagnosis of Resistive Nonvolatile-8T SRAMs	0	0.34	2018
Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM.	0	0.34	2016
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs	0	0.34	2013
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM	1	0.36	2013
Interlaced switch boxes placement for three-dimensional FPGA architecture design	5	0.46	2012
Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications	1	0.35	2012
Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder	3	0.42	2011
A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip.	0	0.34	2010
High-Performance 3d-Sram Architecture Design	4	0.60	2010
Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays	2	0.37	2010
Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications	1	0.37	2010
Built-In Self-Test/Repair Scheme For Tsv-Based Three-Dimensional Integrated Circuits	9	0.56	2010
Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA	7	0.52	2009
Novel Built-In Current-Sensor-Based IDDQ Testing Scheme for CMOS Integrated Circuits.	0	0.34	2009
Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application	3	0.44	2009
A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications	0	0.34	2008
High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC	1	0.37	2007
Design Of Low-Frequency Low-Pass Filters For Biomedical Applications	0	0.34	2006
Design Of Current-Mode Resonator For Wireless Applications	0	0.34	2006
An Adaptive Low-Power Control Scheme for On-Chip Network Applications	0	0.34	2006
New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications	2	0.48	2006
Built-in self-test for phase-locked loops	12	0.88	2005
Frequency-Scaling Approach for Managing Power Consumption in NOCs	3	0.45	2005
Control and Observation Structure for Analog Circuits with Current Test Data	1	0.37	2004