Name
Abstract | ||
|---|---|---|
Abstract: We present a new methodology for designing modulo 2n +1 adders with operands in the diminished-one number system. The proposed methodology leads to parallel-prefix adder implementations. Both an analytical model and VLSI implementations in a standard-cell technology are utilized for comparing the adders designed following the proposed methodology against the existing solutions. Our results indicate that the proposed parallel-prefix adders are considerably faster than any other already known in the open literature and as fast as the corresponding modulo 2 n and modulo 2n-1 adders. |
Year | Venue | Keywords |
|---|---|---|
2001 | IEEE Symposium on Computer Arithmetic | analytical model,proposed parallel-prefix adder,High Speed,adder implementation,corresponding modulo,Diminished-One Operands,open literature,proposed methodology,new methodology,Parallel-Prefix Modulo,diminished-one number system,VLSI implementation,existing solution |
DocType | Citations | PageRank |
Conference | 1 | 0.57 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| H. T. Vergos | 1 | 53 | 11.37 |
| D. Nikolos | 2 | 291 | 31.38 |
| Costas Efstathiou | 3 | 241 | 27.24 |