Paper Info
Title
A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA
Abstract
A 20-MHz bandwidth continuous-time (CT) sigma-delta modulator (SDM) with third-order active-RC loop filter and 4-bit quantizer is implemented in a 0.13-μm CMOS process. The immunity to clock jitter is greatly improved by employing full clock period switched-capacitor-resistor (FSCR) digital-to-analog converter (DAC) for feedback. A new data weighted averaging (DWA) technique is developed to remove the timing bottleneck at 640 MHz clock frequency. The CT SDM achieves 63.9 dB peak signal-to-noise-and-distortion ratio (SNDR) and 68 dB dynamic range (DR) which decreases by only 2.3 dB when the RMS jitter of the 640 MHz clock is 15.6 ps. The power consumption is 58 mW from a 1.2-V supply.
Year
DOI
Venue
2011
10.1109/JSSC.2011.2164296
J. Solid-State Circuits
Keywords
Field
DocType
bandwidth 20 mhz,high-speed dwa,cmos process,cmos integrated circuits,sigma-delta modulation,switched-capacitor-resistor,full clock period scr,data weighted averaging,switched capacitor filters,power consumption,voltage 1.2 v,jitter immunity,continuous-time sigma-delta modulator,frequency 640 mhz,quantizer,low-power electronics,third-order active-rc loop filter,signal-to-noise-and-distortion ratio,clocks,rms jitter,clock jitter,time 15.6 ps,active filters,dac,switched-capacitor resistor (scr) feedback,power 58 mw,size 0.13 mum,digital-to-analog converter,digital-analogue conversion,modulation,switched capacitor,low power electronics,jitter,thyristors,dynamic range,noise,sigma delta modulator
Dynamic range,Active filter,Computer science,Control theory,CMOS,Delta-sigma modulation,Electronic engineering,Bandwidth (signal processing),Jitter,Clock rate,Low-power electronics
Journal
Volume
Issue
ISSN
46
11
0018-9200
Citations 
PageRank 
References 
9
0.80
6
Authors
3
Name
Order
Citations
PageRank
Jun-Gi Jo1192.37
Jinho Noh2171.68
Changsik Yoo311634.39