Name
Abstract | ||
|---|---|---|
In this paper we propose a new Test Pattern Generator (TPG) for the detection of realistic faults occurring in CMOS nanometer technologies. The proposed TPG compares favorably to the corresponding already known TPGs with respect to the fault coverage obtained by test sequences of the same length. Another advantage of the proposed TPG is that the same TPG can be used for testing more than one modules in a SOC. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/988952.989052 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
cmos nanometer technology,new test pattern generator,bist environment,high defect coverage,realistic fault,proposed tpg,test sequence,fault coverage,stuck at fault | Stuck-at fault,Fault coverage,Computer science,Electronic engineering,Test pattern generators,CMOS,Real-time computing,Built-in self-test | Conference |
ISBN | Citations | PageRank |
1-58113-853-9 | 3 | 0.42 |
References | Authors | |
7 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. Laoudias | 1 | 6 | 1.37 |
| D. Nikolos | 2 | 291 | 31.38 |