Paper Info
Title
A Gb/s+ slew-rate/impedance-controlled output driver with single-cycle compensation time
Abstract
This brief introduces a low-noise slew-rate/ impedance-controlled high-speed output driver in 0.18-µm CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.1-3.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.
Year
DOI
Venue
2010
10.1109/TCSII.2009.2038631
IEEE Trans. on Circuits and Systems
Keywords
DocType
Volume
impedance-controlled output driver,pseudo-open-drain output driver,output driver,driver impedance,single-cycle compensation time,data slew rate,control block,low-noise slew-rate,signal slew-rate,proposed scheme,impedance-controlled high-speed output driver,proposed output driver
Journal
57
Issue
ISSN
Citations 
2
1549-7747
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Young-Ho Kwak1446.75
Inhwa Jung27011.23
Chulwoo Kim339774.58