Name
Abstract | ||
|---|---|---|
The proposed voltage scheme adaptively tunes the supply voltage of digital circuits, according to PVTA variations. By exploiting unused timing margin, produced by state-of-the-art worst-case designs, energy efficiency is significantly increased. In-situ delay monitoring is performed by enhanced flip-flops, observing signal delays in critical paths. We introduce a novel methodology to analyze the closed-loop behavior of the overall control scheme by a Markov approach, based on extensive transistor simulations. The digital logic and the AVS control circuitry are designed in 65nm CMOS for an image processing application. The AVS approach optimizes dynamic and leakage power dependent on the user-defined image quality requirements. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/DDECS.2012.6219058 | Design and Diagnostics of Electronic Circuits & Systems |
Keywords | Field | DocType |
CMOS integrated circuits,Markov processes,flip-flops,image processing,logic design,AVS control circuitry,CMOS,Markov approach,PVTA variation,adaptive voltage scaling,closed-loop behavior,delay monitoring,digital circuit,digital logic,dynamic power,energy efficiency,extensive transistor simulation,flip-flops,image processing circuit,leakage power,size 65 nm,timing margin,user-defined image quality | Logic synthesis,Digital electronics,Markov process,Timing margin,Computer science,Image processing,Image quality,Electronic engineering,Real-time computing,CMOS,Transistor | Conference |
ISSN | ISBN | Citations |
2334-3133 | 978-1-4673-1186-1 | 3 |
PageRank | References | Authors |
0.52 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Martin Wirnshofer | 1 | 11 | 1.81 |
| Leonhard Heiß | 2 | 9 | 1.04 |
| Anil Narayan Kakade | 3 | 3 | 0.52 |
| Nasim Pour Aryan | 4 | 47 | 7.67 |
| Georg Georgakos | 5 | 84 | 8.10 |
| Doris Schmitt-landsiedel | 6 | 260 | 50.73 |
| Heiss, L. | 7 | 4 | 0.88 |