Name
Abstract | ||
|---|---|---|
For system-level verification of a large-scale design, logic simulation is widely used. When a simulation trace exposes a design error a designer may rectify the design inadequately because the trace shows only one particular erroneous path. This is one of the essential problems of simulation based verification. On the other hand, model checkers are becoming widely used in industry but cannot verify large designs. We propose a new verification methodology based on a “navigated” model checking in order to overcome the above problems. We first generalize the trace and generate a property. We then verify the rectified design against the property by navigating state traversal in model checking. With navigation, we can verify designs without ad-hoc simplification and also can check various possible paths relating the error, instead of concentrating on a particular path of the trace. We have successfully verified bus transactions of a system-on-a-chip having two million transistors with our methodology. For one case, we found that the rectification was inadequate, and we fixed it successfully |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ICCD.1998.727066 | International Conference on Computer Design |
Keywords | Field | DocType |
system-level verification,logic simulation,logic cad,model checking,custom circuit,large scale system-on-a-chip,small team,symbolic model checking,custom datapath circuit technology,ibm austin research laboratory,gigahertz microprocessor,dynamic array control structure,formal verification,testing,reactive power,very large scale integration,system on a chip,logic design,navigation,chip | Formal equivalence checking,Abstraction model checking,Functional verification,Model checking,Computer science,Real-time computing,Logic simulation,High-level verification,Formal verification,Symbolic trajectory evaluation | Conference |
ISSN | ISBN | Citations |
1063-6404 | 0-8186-9099-2 | 8 |
PageRank | References | Authors |
2.36 | 8 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kazuyoshi Takayama | 1 | 13 | 4.70 |
| Satoh, T. | 2 | 8 | 2.36 |
| Nakata, T. | 3 | 8 | 2.36 |
| Fumiyasu Hirose | 4 | 258 | 97.57 |