Name
Abstract | ||
|---|---|---|
The excessive interconnection delay and fast increasing development cost, as well as complexity of the single-chip integration of different technologies, are likely to become the major stumbling blocks for the success of monolithic system-on-chips. To address the above problems, this paper investigates a new VLSI integration paradigm, the so-called 2.5-dimensional (2.5-D) integration scheme. Using this scheme, a VLSI system is implemented as a three-dimensional stacking of monolithic chips. A cost analysis framework was developed to justify the 2.5-D integration scheme from an economic point of view. Enabling technologies for the new integration scheme are also reviewed. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/TVLSI.2005.848814 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
vlsi system integration,new integration scheme,integration scheme,enabling technology,vlsi system,cost analysis framework,single-chip integration,development cost,new vlsi integration paradigm,monolithic system-on-chips,monolithic chip,three dimensional,system integration,cost analysis,system on a chip,chip,system on chip,cmos technology,very large scale integration,fabrication,vlsi | System on a chip,Computer science,CMOS,Electronic engineering,Three dimensional model,Cost analysis,Interconnection,Integrated circuit,Very-large-scale integration,System integration | Journal |
Volume | Issue | ISSN |
13 | 6 | 1063-8210 |
Citations | PageRank | References |
9 | 1.12 | 30 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yangdong Deng | 1 | 429 | 44.78 |
| Wojciech Maly | 2 | 1976 | 352.57 |