Name
Abstract | ||
|---|---|---|
In conventional delay testing, two types of tests, transition tests and path delay tests, are often considered. The test clock frequency is usually set to a single pre-determined parameter equal to the system clock. This paper discusses the potential of enhancing test effectiveness by using multiple test sets with multiple clock frequencies. The two intuitions motivating our analysis are 1) multiple test sets can deliver higher test quality than a single test set, and 2) for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out potentially defective chips. Hence, by using multiple test sets, the overall quality of AC delay test can be enhanced, and by using multiple-clock schemes the cost of adding the additional pattern sets can be minimized. In this paper, we analyze the feasibility of this new delay test methodology with respect to different combinations of pattern sets and to different circuit characteristics. We discuss the pros and cons of multiple-clock schemes through analysis and experiments using a statistical delay evaluation and delay defect-injected framework. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/TEST.2002.1041786 | ITC |
Keywords | Field | DocType |
delay test effectiveness,integrated circuit testing,critical path test patterns,test clock frequency,multiple test set,multiple test sets,statistical delay evaluation,delay defect-injected framework,path delay test,higher test quality,automatic test pattern generation,timing,delays,delay test methodology,vlsi,ac delay patterns,pattern sets,transition fault patterns,multiple clock frequencies,new delay test methodology,test effectiveness,multiple-clock scheme,transition tests,transition test,ac delay test,single test set,path delay tests,logic testing,chip,robustness,multiple testing,pattern analysis | Delay calculation,Test method,Automatic test pattern generation,Computer science,Electronic engineering,Real-time computing,Static timing analysis,Test compression,Clock rate,Asynchronous circuit,Test set | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-7542-4 | 6 |
PageRank | References | Authors |
0.78 | 15 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jing-Jia Liou | 1 | 552 | 64.27 |
| Li-C. Wang | 2 | 527 | 50.67 |
| Kwang-Ting Cheng | 3 | 5755 | 513.90 |
| Jennifer Dworak | 4 | 132 | 11.63 |
| M. Ray Mercer | 5 | 679 | 108.73 |
| Rohit Kapur | 6 | 815 | 74.50 |
| Thomas W. Williams | 7 | 177 | 17.30 |