Name
Title | ||
|---|---|---|
A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS |
Abstract | ||
|---|---|---|
Flip-flops (FF) typically consume more than 50% of random-logic power in an SoC chip, due to their redundant transition of internal nodes, when the input and the output are in the same state. Several low-power techniques have been proposed, but all of them incur transistor-count penalties, leading to an increase in size, which is too costly since flip-flops typically account for 50% of random-logic area. In this work, we design and test a D-flip-flop, known as adaptive-coupling flip-flop (ACFF), which has a reduced transistor count compared to other low-power flip-flops, and 2 fewer transistors than the mainstream transmission-gate flip-flop (TGFF). ACFF features a single-phase clocking structure, with no local clock buffer and no precharging stage, enabling it to be more energy efficient than TGFF, where up to 77% energy saving is achieved at 0% data activity. ACFF also has an adaptive-coupling configuration, which weakens state retention coupling during a transition, allowing it to be tolerant to process variations. Test chips are fabricated in a 40nm CMOS technology for 1.1V application, and 500k ACFFs are tested over all chips in 5 skew wafers. All tested ACFFs are fully functional down to 0.75V supply voltage, with spreads of timing parameters comparable to TGFF. We also demonstrate a P&R test by employing ACFF to a wireless LAN chip, and the results indicate chip power is reduced by as much as 24%. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISSCC.2011.5746344 | ISSCC |
Keywords | Field | DocType |
transistor-count penalty,cmos integrated circuits,low-power flip-flop,integrated circuit testing,adaptive-coupling configuration,p&r test,state retention coupling,reduced transistor count,transmission-gate flip-flop,size 40 nm,timing parameter,energy saving,low-power electronics,test chip,cmos technology,adaptive-coupling flip-flop,soc chip,logic design,integrated circuit design,single-phase-clocking d-flip-flop,low-power technique,flip-flops,random-logic power,random-logic area,voltage 1.1 v,data activity,wireless lan chip,logic testing,semiconductor devices,chip,logic gate,energy efficient,low power electronics,transistors,process variation,logic gates | Transistor count,Logic gate,Computer science,CMOS,Electronic engineering,Chip,Integrated circuit design,Flip-flop,Transistor,Electrical engineering,Low-power electronics | Conference |
ISSN | ISBN | Citations |
0193-6530 | 978-1-61284-303-2 | 16 |
PageRank | References | Authors |
1.23 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chen Kong Teh | 1 | 39 | 4.66 |
| Tetsuya Fujita | 2 | 62 | 14.04 |
| Hiroyuki Hara | 3 | 67 | 7.06 |
| Mototsugu Hamada | 4 | 130 | 22.06 |