Name
Abstract | ||
|---|---|---|
Dynamic test sequence compaction is an effective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. Three simulation-based techniques for dynamic compaction of test sequences are described. The first technique uses a fault simulator to remove test vectors from the test sequence generated by a test generator if the vectors are not needed to detect the target fault, considering that the circuit state may be known. The second technique uses genetic algorithms to fill the unspecified bits in a partially-specified test sequence in order to increase the number of faults detected by the sequence. The third technique uses test sequences provided by the test generator as seeds in a genetic algorithm, and better sequences are evolved that detect more faults. Significant improvements in test set size, fault coverage, and test generation time have been obtained over previous approaches using combinations of the three techniques. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/12.754998 | IEEE Trans. Computers |
Keywords | Field | DocType |
test vector,test application time,efficient techniques,dynamic test sequence compaction,genetic algorithm,test set size,test generation time,reduced test generation time,partially-specified test sequence,test generator,test sequence,sequential circuits,sequential analysis,compaction,genetic algorithms,fault detection,fault coverage | Stuck-at fault,Automatic test pattern generation,Fault coverage,Dynamic compaction,Computer science,Algorithm,Real-time computing,Dynamic testing,Fault Simulator,Test compression,Test set | Journal |
Volume | Issue | ISSN |
48 | 3 | 0018-9340 |
Citations | PageRank | References |
16 | 0.74 | 25 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Elizabeth M. Rudnick | 1 | 867 | 76.37 |
| J. H. Patel | 2 | 4577 | 527.59 |