An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Paper Info

Title
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Abstract
4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/O, power supply noise, and crosstalk. Both DBI AC and DC modes are combined to a single circuit by eliminating the feedback path of a conventional DBI...

Year	DOI	Venue
2008	10.1109/JSSC.2007.908002	IEEE Journal of Solid-State Circuits
Keywords	Field	DocType
Graphics,Random access memory,Crosstalk,Feedback circuits,Jitter,SDRAM,CMOS process,Energy consumption,Power supplies,Circuit noise	Dynamic random-access memory,Single-ended signaling,Computer science,Voltage,Electronic engineering,Power electronics,Jitter,Electrical engineering,Integrated circuit,System bus,Low-power electronics	Journal
Volume	Issue	ISSN
43	1	0018-9200
Citations	PageRank	References
22	5.33	9
Authors
24

Authors (24 rows)

Cited by (22 rows)

References (9 rows)

Name	Order	Citations	PageRank
Seung-Jun Bae	1	167	32.40
Kwang-Il Park	2	163	25.68
Jeong-Don Ihm	3	65	10.22
Ho-Young Song	4	39	9.78
Woojin Jin	5	144	22.37
Jin Hyun Kim	6	92	21.61
Kyoung-Ho Kim	7	56	11.87
Yoon-Sik Park	8	22	5.67
Min-Sang Park	9	66	13.05
Hong-Kyong Lee	10	22	5.33
Sam-Young Bang	11	63	13.01
Gil-Shin Moon	12	61	11.93
Seokwon Hwang	13	81	14.51
Youngchul Cho	14	87	13.10
Sang-Jun Hwang	15	29	12.67
Dae Hyun Kim	16	505	46.95
Ji-hoon Lim	17	29	7.64
Jae Sung Kim	18	96	18.57
Sung-Hoon Kim	19	22	5.67
Seong-jin Jang	20	99	27.16
Joo Sun Choi	21	239	24.11
Young-Hyun Jun	22	22	5.67
Kinam Kim	23	178	55.87
Soo-In Cho	24	142	36.44