Paper Info
Title
6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers
Abstract
Solid-state drives (SSDs), built with many flash memory channels, is usually connected to the host through an advanced high-speed serial interface such as SATA III associated with a transfer rate of 6Gb/s [1-2]. However, the performance of SSD is in general determined by the throughput of the ECC blocks necessary to overcome the high error-rate [3]. The binary BCH code is widely used for the SSD due to its powerful error-correction capability. As it is hard to achieve high-throughput strong BCH decoders [4-5], multiple BCH decoders are typically on a high-performance SSD controller, leading to a significant increase of hardware complexity. This paper presents an efficient BCH encoder/decoder architecture achieving a decoding throughput of 6Gb/s. The overall architecture shown in Fig. 25.3.1 includes a single BCH decoder and a multi-threaded BCH encoder. The single BCH encoder is responsible for all the channels and services a channel at a time in a round-robin manner.
Year
DOI
Venue
2012
10.1109/ISSCC.2012.6177075
ISSCC
Keywords
Field
DocType
solid-state drives,decoder,bit rate 6.4 gbit/s,flash memory channels,high-speed serial interface,hardware complexity,bch codes,multi-channel ssd controllers,encoding,round-robin manner,error correction codes,sata iii,error-correction capability,binary codes,binary bch code,multi-threaded bch encoder,high error-rate,decoding,flash memories,bch code,prototypes,hardware,high throughput,error correction,throughput,error rate,computer architecture
Flash memory,Computer science,Parallel computing,Binary code,Communication channel,BCH code,Encoder,Throughput,Decoding methods,Computer hardware,Encoding (memory)
Conference
ISSN
ISBN
Citations 
0193-6530
978-1-4673-0376-7
17
PageRank 
References 
Authors
1.21
4
4
Name
Order
Citations
PageRank
Youngjoo Lee17418.85
Hoyoung Yoo2759.99
Injae Yoo3275.26
In-Cheol Park4888124.36