Hoyoung Yoo - Citegraph

Author Info

Name	Affiliation	Papers
HOYOUNG YOO	Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea	18
Collaborators	Citations	PageRank
11	75	9.99
Referers	Referees	References
199	196	76

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100199

Publications (18 rows)

Collaborators (11 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism	1	0.36	2021
On-demand Syndrome Calculation for BCH decoding	0	0.34	2019
Resource usage of LTE networks for machine-to-Machine group communications: Modeling and analysis.	0	0.34	2018
Hybrid Decoding for Polar Codes	0	0.34	2018
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems	4	0.51	2016
Efficient Pruning for Successive-Cancellation Decoding of Polar Codes.	0	0.34	2016
Low-Power Parallel Chien Search Architecture Using a Two-Step Approach.	2	0.45	2016
Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes.	5	0.53	2016
Partially Parallel Encoder Architecture for Long Polar Codes	11	0.66	2015
Efficient Parallel Architecture for Linear Feedback Shift Registers	2	0.44	2015
7.3 Gb/s universal BCH encoder and decoder for SSD controllers	4	0.56	2014
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives	0	0.34	2014
Area-Efficient Multimode Encoding Architecture for Long BCH Codes	6	0.68	2013
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory	5	0.52	2013
A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13µm CMOS process.	0	0.34	2013
6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers	17	1.21	2012
Low-latency area-efficient decoding architecture for shortened reed-solomon codes	7	0.94	2012
Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization	11	1.10	2011

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