Name
Abstract | ||
|---|---|---|
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. In this paper we describe a new technique of property checking using symbolic simulation which can be applied to larger designs. This technique seamlessly integrate formal verification and standard simulation. The proposed method is a formal verification technique which checks symbolically a given LTL specification against the Hardware Design. Our experimental results show a run time gain over standard symbolic model checking and SAT-based bounded model checking for certain classes of circuits and properties. |
Year | Venue | Keywords |
|---|---|---|
2003 | FDL | digital design,formal verification,formal method,system design |
Field | DocType | Citations |
Formal equivalence checking,Symbolic simulation,Abstraction model checking,Model checking,Programming language,Computer science,Theoretical computer science,Design rule checking,Formal methods,Symbolic trajectory evaluation,Formal verification | Conference | 0 |
PageRank | References | Authors |
0.34 | 15 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jürgen Ruf | 1 | 122 | 23.04 |
| Prakash Mohan Peranandam | 2 | 7 | 2.64 |
| Thomas Kropf | 3 | 326 | 59.09 |
| Wolfgang Rosenstiel | 4 | 1462 | 212.32 |