Name
Abstract | ||
|---|---|---|
In this paper, we propose a new physical synthesismethodology, PDL, which relaxes the timing constraintsto obtain best optimality in terms of layout quality andtiming quality. It provides a common database for delaycalculation, logic optimization, placement, and routingtools so that they can work and interact closely. Wepresent results on industrial circuits showing the efficacyof this methodology. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ISQED.2003.1194757 | ISQED |
Keywords | Field | DocType |
new physical synthesis methodology,common database,layout quality,logic optimization,best optimality,wepresent result,industrial circuit,new physical synthesismethodology,delay calculation,integrated circuit design,network routing,new physics,critical path analysis,integrated circuit layout,logic,design optimization,routing,pdl,logic design | Logic synthesis,Integrated circuit layout,Delay calculation,Logic optimization,Computer science,Electronic engineering,Real-time computing,Integrated circuit design,Critical path method,Physical synthesis,Electronic circuit | Conference |
ISBN | Citations | PageRank |
0-7695-1881-8 | 0 | 0.34 |
References | Authors | |
12 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toshiyuki Shibuya | 1 | 89 | 11.80 |
| Rajeev Murgai | 2 | 342 | 55.69 |
| Tadashi Konno | 3 | 0 | 0.34 |
| Kazuhiro Emi | 4 | 0 | 0.34 |
| Kaoru Kawamura | 5 | 13 | 1.80 |