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| Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019. | 0 | 0.34 | 2019 |
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| Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances | 3 | 0.42 | 2010 |
| B-escape: a simultaneous escape routing algorithm based on boundary routing | 10 | 0.58 | 2010 |
| Efficiently finding the ‘best’ solution with multi-objectives from multiple topologies in topology library of analog circuit | 3 | 0.40 | 2009 |
| Find The 'Best' Solution From Multiple Analog Topologies Via Pareto-Optimality | 0 | 0.34 | 2009 |
| Efficient Power Network Analysis Considering Multidomain Clock Gating | 4 | 0.50 | 2009 |
| Non-Gaussian statistical timing models of die-to-die and within-die parameter variations for full chip analysis | 4 | 0.62 | 2008 |
| Finding the worst voltage violation in multi-domain clock gated power network | 2 | 0.42 | 2008 |
| Fast power network analysis with multiple clock domains | 8 | 1.14 | 2007 |
| Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? | 0 | 0.34 | 2005 |
| PDL: A New Physical Synthesis Methodology | 0 | 0.34 | 2003 |
| Large scale circuit partitioning with loose/stable net removal and signal flow based clustering | 45 | 3.72 | 1997 |
| Touch and cross router | 8 | 0.86 | 1990 |
