Paper Info
Title
A static estimation technique of power sensitivity in logic circuits
Abstract
In this paper, we study a new problem of statically estimating the power sensitivity of a given logic circuit with respect to the primary inputs. The power sensitivity defines the characteristics of power dissipation due to changes in state of primary inputs, Consequently, estimating the power sensitivity among the inputs is essential not only to measure the power consumption of the circuit efficiently but also to provide potential opportunities of redesigning the circuit for low power, In this context, we propose a fast and reliable static estimation technique for power sensitivity based on a new concept called power equations, which are then collectively transformed into a table called power table. Experimental data on MCNC benchmark examples show that the proposed technique is useful and effective in estimating power consumption. In summary, the relative error for the estimation of maximum power consumption is 9.4% with a huge speed-up in simulation.
Year
DOI
Venue
2001
10.1109/DAC.2001.156138
DAC
Keywords
Field
DocType
maximum power consumption,new concept calledpower equation,logic circuits,new problem,power equations,logic simulation,primary input,proposed technique,power consumption,combinational circuits,power dissipation,circuit optimisation,low-power electronics,power sensitivity,vlsi,integrated circuit design,low power,static estimation technique,logic circuit,mcnc benchmark examples,sensitivity analysis,low power electronics,relative error,power system simulation,power generation
Power gain,Logic gate,Computer science,Electronic engineering,Combinational logic,Real-time computing,Logic simulation,Integrated circuit design,Maximum power principle,Very-large-scale integration,Low-power electronics
Conference
ISSN
ISBN
Citations 
0738-100X
1-58113-297-2
1
PageRank 
References 
Authors
0.37
7
3
Name
Order
Citations
PageRank
Taewhan Kim11087113.31
Ki-seok Chung218918.76
C. L. Liu36191970.79