Name
Abstract | ||
|---|---|---|
The settling behavior of switched-capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two-stage Miller-compensated operational amplifiers (op-amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op-amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35- µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright © 2010 John Wiley & Sons, Ltd. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1002/cta.687 | I. J. Circuit Theory and Applications |
Keywords | Field | DocType |
conventional design approach,design criterion,classical strategy,optimization strategy,sc circuit,high-speed low-power sc circuit,small capacitive,design example,advanced circuit model,typical sc circuit,significant settling time reduction,frequency compensation,settling time,operational amplifiers | Settling,Capacitance,Settling time,Control theory,Electronic engineering,Capacitive sensing,CMOS,Electronic circuit,Frequency compensation,Electrical engineering,Operational amplifier,Mathematics | Journal |
Volume | Issue | ISSN |
39 | 10 | 0098-9886 |
Citations | PageRank | References |
0 | 0.34 | 17 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. A. Amoroso | 1 | 6 | 3.70 |
| A. Pugliese | 2 | 115 | 12.90 |
| Gregorio Cappuccino | 3 | 36 | 10.11 |