Gregorio Cappuccino

Author Info

Name	Affiliation	Papers
GREGORIO CAPPUCCINO	Department of Electronics, Computer Science and Systems, University of Calabria Arcavacata di Rende, 87036 Rende (CS), Italy	23
Collaborators	Citations	PageRank
17	36	10.11
Referers	Referees	References
67	177	117

Search Limit

100177

Publications (23 rows)

Collaborators (17 rows)

Referers (67 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier.	0	0.34	2014
A new efficient SC integrator scheme for high-speed low-power applications	2	0.40	2012
Design approach for high-bandwidth low-power three-stage operational amplifiers	1	0.39	2012
Design criterion for high-speed low-power SC circuits	0	0.34	2011
Corrections to "settling time optimization for three-stage CMOS amplifier topologies"	0	0.34	2010
Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance	0	0.34	2010
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances	3	0.55	2010
Corrections to “Settling Time Optimization for Three-Stage CMOS Amplifier Topologies” [Dec 09 2569-2582]	0	0.34	2010
Class-AB output stage design for high-speed three-stage op-amps	0	0.34	2009
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies	9	1.33	2009
Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances.	0	0.34	2009
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers	16	0.87	2008
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers	0	0.34	2008
Integrated waveguides for ultra-high speed interconnects.	0	0.34	2007
Correct modelling of nested miller compensated amplifier for discrete-time applications	0	0.34	2006
A simple MOSFET parasitic capacitance model and its application to repeater insertion technique	0	0.34	2006
Output resistance scaling model for deep-submicron cmos buffers for timing performance optimisation	0	0.34	2005
Operating mode analysis of deep-submicron CMOS buffers driving inductive interconnects	0	0.34	2003
Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects	0	0.34	2003
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines	2	0.77	2002
CMOS sizing rule for high performance long interconnects	1	0.36	2001
A time-domain model for power dissipation of CMOS buffers driving lossy transmission lines	0	0.34	1999
High performance VLSI modules for division and square root	2	0.37	1998