Title
Pipelined Architecture for Additive Range Reduction
Abstract
Range reduction is a crucial step for the accuracy in trigonometric functions evaluation. A new pipelined architecture to deal with range reduction for floating point representation is presented in this paper. The algorithm is based on a look-up table storing the corresponding powers of 2 mod A. The overall design has been optimized for a modulo equal to 2驴, which is the most widely used due to trigonometric functions requirements. We provide an evaluation of different configurations and a full error propagation study which ensures an accuracy of one unit in the last place.
Year
DOI
Venue
2008
10.1007/s11265-008-0166-x
Signal Processing Systems
Keywords
Field
DocType
pipelined architecture,range reduction,modular arithmetic,floating-point,redundant arithmetic
Architecture,Trigonometric functions,Propagation of uncertainty,Modulo,Floating point,Computer science,Modular arithmetic,Parallel computing,Arithmetic,Algorithm,Unit in the last place
Journal
Volume
Issue
ISSN
53
1-2
1939-8018
Citations 
PageRank 
References 
2
0.44
4
Authors
4
Name
Order
Citations
PageRank
Francisco J. Jaime1163.92
Julio Villalba221923.56
Javier Hormigo311319.45
Emilio L. Zapata4811100.36